Architectural requirements of image understanding with respect to parallel processing
Article Abstract:
Both sensory and knowledge-based processing are involved in vision, but it is helpful to have one or more levels of symbolic processing between these two levels of abstraction. Algorithms and representations are divided into three levels: low, sensory; intermediate, symbolic; and high, knowledge-based. A computer vision system must encompass these three sets of requirements. There are three categories of requirements at each level: computation, related to the operations and data types; communication, which depends on the type of data used and how it is manipulated; and control, which is based on the algorithmic control and data structures and the interdependencies between and within levels. Because of these three distinct levels of abstraction, a homogeneous parallel processor is not suitable, a heterogeneous processor should be considered.
Publication Name: Proceedings of the IEEE
Subject: Electronics
ISSN: 0018-9219
Year: 1991
User Contributions:
Comment about this article or add new information about this topic:
A comparison of shared and nonshared memory models of parallel computation
Article Abstract:
Performance is the single goal of parallel computation, but the costs involved must also be considered. Four algorithms are analyzed to determine the predicted performance when used on shared and nonshared memory models of parallel computers. The results of the tests show that the nonshared memory model is accurate, the programs are realizable. The tests show that local memory programs have the best realizable performance. The shared memory model results in algorithms that cannot be realized on any physical parallel computer.
Publication Name: Proceedings of the IEEE
Subject: Electronics
ISSN: 0018-9219
Year: 1991
User Contributions:
Comment about this article or add new information about this topic:
Faster Parallel Multiplier
Article Abstract:
A parallel multiplier increases computation speed and reduces logic complexity by reducing the length of the carry look-ahead adder. The improvement is over Dadda's original schemes. Diagrams illustrate the multipliers, and data are given which compare the schemes.
Publication Name: Proceedings of the IEEE
Subject: Electronics
ISSN: 0018-9219
Year: 1984
User Contributions:
Comment about this article or add new information about this topic:
- Abstracts: Disk system architectures for high performance computing. Parallel architectures for vision
- Abstracts: A Processor Family for Personal Computers. Computing image texture features in parallel computers
- Abstracts: Least-square identification with error bounds for real-time signal processing and control. Error Probability in Nakagami-Rice Channel