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Array architectures for iterative algorithms

Article Abstract:

Regular mesh-connected arrays are analyzed and found to be isomorphic to a class of regular iterative algorithms, and the method by which algorithms can be translated into arrays is demonstrated as systematic. Several generally recognized systolic arrays are demonstrated to be specific cases of the types of architectures that can be derived by techniques presented, including arrays for Fourier transform, matrix multiplication, and sorting. The technique can be fully automated, produces multiple choices for algorithms, allows regularly iterative algorithms to be mapped into fixed-size mesh-connected processor arrays, and handles a large class of algorithms.

Author: Jagadish, Hosagrahar, V., Rao, Sailesh K., Kailath, Thomas
Publisher: Institute of Electrical and Electronics Engineers, Inc.
Publication Name: Proceedings of the IEEE
Subject: Electronics
ISSN: 0018-9219
Year: 1987
Sorting, Mathematical Proofs, Matrix Computations, Arrays, Fast Fourier Transforms, technical, Mesh Networks

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Task-Oriented Architectures

Article Abstract:

The factory of the future is a concept of an essentially peopleless, paperless organization. The factory should be capable of producing a wide variety of parts on demand. Speech recognition, speech synthesis and image processing tasks are examples of sensor-interpretation problems. These problems require the development of special purpose processors. A number of issues are to be considered while designing task-oriented systems. A block diagram shows architecture of the Harpy machine.

Author: Reddy, R., Bisiani, R., Mauersberg, H.
Publisher: Institute of Electrical and Electronics Engineers, Inc.
Publication Name: Proceedings of the IEEE
Subject: Electronics
ISSN: 0018-9219
Year: 1983
Software, Technology, Image processing, Design, Hardware, Task analysis, Evaluation, Factory management, Future Technologies

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Advanced parallel processing with supercomputer architectures

Article Abstract:

Parallel processing techniques and new architectures can boost supercomputer performance. Performance enhancement methods, parallel algorithms, the programming environment, control of concurrency, resource management, compiling techniques, parallel languages, and architectural choices are evaluated for the best solution.

Author: Hwang, Kai
Publisher: Institute of Electrical and Electronics Engineers, Inc.
Publication Name: Proceedings of the IEEE
Subject: Electronics
ISSN: 0018-9219
Year: 1987
Architecture, Supercomputers, Supercomputer, Parallel processing, Performance improvement (Computers), Performance Improvement

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Subjects list: Algorithms, Algorithm
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