Memory systems for highly parallel computers

Article Abstract:

SIMD systems have a number of problems, such as inflexibility in memory addressing; inefficiency in numerical operations; slowness in routing data; input and output bottlenecks; and an iconic/symbolic gap in computer vision problems. These problems can be handled by increasing memory capacity and speed and increasing functionality. An improved memory system can improve the numerical capabilities of SIMD arrays by supporting indexed addressing to permit efficient table lookup, handling the corner-turning function, and maximizing the utilization of narrow memory channels between processing elements and memory. Throughput can be increased by tightly integrating routing and memory. A better use of memory will simplify and accelerate input and output. An application-specific memory chip that permits data to be accessed on either of two ports, where one port is bitmap oriented and one port is symbol oriented, has been developed at the University of Washington. This bimodal memory system makes it possible to use a variety of ways to allocate work to either the SIMD or the microprocessors. This system is called the PIRAM chip; it has 64 random-access memory modules of 1 bit by 4096 locations.

Research, Integrated circuits, Microprocessor, CPUs (Central processing units), Memory, Washington, University of, Parallel processing, I/O Management, I/O management (Computers), Arrays, technical, Massive Parallelism, SIMD

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Limits of nano-gate fabrication

Article Abstract:

The limits of nanometer scale gate electrode (nano-gate) fabrication are reviewed. The technology involved in fabricating nano-gates is increasing in importance as a result of research on the scaling limits of conventional electronic devices and the quantum effects of novel devices. Emphasis is placed on the resolution limits of electron beam lithography and associated ultrahigh resolution resists, consistent with the technology used to fabricate virtually all of the smallest devices currently available. The results of directly patterning SiO(subscript 2) with nanometer scale resolution by e-beam exposure through a sacrificial layer are presented. Various techniques for reducing gate resistance are compared.

Integrated circuit fabrication, Industrial research, Electronics, Nanotechnology, Technical, Research and Development, Gates

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