Dynamic RAM as secondary cache

Article Abstract:

Cache DRAM can play a key role in offsetting the deleterious effect of cache misses on system performance as processor clock frequencies rise by providing a second-level cache that complements the on-chip cache. Access time and hit rate are the most important parameters for a secondary cache, and secondary cache speed must be as great as possible and its hit rate optimized. Hit rate is optimized by including a small static RAM and linking its dynamic and static sections by a wide data path. A cache DRAM has the potential to improve processor utilization by 42 percent. It can also boost hit rate to 96.9 percent. In addition, the Cache DRAM architecture allows the small memory involving access time to function like a large one.

Usage, Circuit design, Dynamic random access memory, DRAM (Dynamic random access memory), Cache memory, Processor speeds, Performance improvement (Computers), DRAM, Functional Capabilities, Processor Speed, Performance Improvement

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Hologram lenses lead to compact scanners

Article Abstract:

Increased use and demand for bar code scanners in stores and production facilities have created a highly competitive market and fueled R&D funds to improve them. Work on a new type of laser beam using holography stems from this. The result is that new point-of-sale (POS) scanners using the holographic versions are able to read bar codes at any angle and at high speed. They provide the technological key to improving the speed and accuracy of reading Universal Product Codes. A history of bar code scanners and a description of their design and construction and varied uses is provided. Useful sources for further reading are given.

Computer peripheral equipment, not elsewhere classified, Research, Industrial research, Product development, Bar code scanners, Fujitsu Laboratories Ltd., Holography, Research and Development, Scanning, Low Cost, POS Systems, Barcode/Mark Reader

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