Cascaded VLSI neural network chips: hardware learning for pattern recognition and classification

Article Abstract:

Currently map data is stored as high-resolution digitized pixel data on CD-ROM storage devices. The copious amount of data generated from the global map data base overwhelms even high-density optical storage methods. In addition, the map user is concerned not with the high-resolution image of the map, but the actual features such as roads and rivers. By classifying the map-image pixels into separate features, the dimensionality of the data is dramatically reduced, the map is significantly decluttered, and the data is in the form most suitable for further analysis. Because of the extensive volume of the data already stored and its on-demand nature, classification speed must exceed the CD-ROM read speed so that access rates are unaffected. This paper describes a neural network approach to pattern classification applied to map pixel data. Software simulations of a sophisticated neural network show that neural networks are indeed equivalent to optimal statistical pattern classifiers. Furthermore, a fully parallel neural network hardware implementation developed at JPL, surpasses the necessary processing speed, and provides high classification accuracy. Our software as well as hardware results are presented in this paper along with a brief background in pattern classification and neural networks. (Reprinted by permission of the publisher.)

Pattern recognition (Computers), Industrial research, Neural networks, CD-ROM disks, Maps (Geography), Pixels, Very large scale integration, Research and Development, Pattern Recognition, Data Analysis, Computer Learning, Enhancements, Classification Systems, Access Time, Maps, Very-Large-Scale Integration, Neural Network, CD-ROM

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Investigating simulation of hardware at various levels of abstraction and timing back-annotation of dataflow descriptions

Article Abstract:

Digital hardware can be described at various levels of abstraction. Functional descriptions merely capture the behavior of the circuit without revealing the details of the architecture. On the other hand, the gate or switch level models are more robust and include great amounts of detail about the circuit (timing and architecture). Functional models are attractive because they simulate faster than low level models. However, the tradeoff is that the simulation results are not as accurate (primarily from the timing standpoint) as those obtained from low level models. Clearly, having a model that simulates as fast as the functional model and produces accuracies comparable to those of gate level models is desirable. This paper is an investigation of achieving such models. Two levels of abstractions, dataflow and gate level, are considered and the VHDL language (an industry standard) is used for describing Finite State Machine circuits at both levels. Feasibility of timing back-annotation of dataflow models with information obtained from gate level is analyzed. (Reprinted by permission of the publisher.)

Circuit design, Models, Hardware Description Language, Data Flow Diagrams, Timing Circuitry, Finite State Automata

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