Wafer level burn-in

Article Abstract:

Motorola Semiconductor Products Sector, Tokyo Electron Limited (TEL) of Japan, and W.L. Gore of Eau Claire, WI, have developed a new wafer burn-in technology following an 18-month collaborative initiative. Originally designed to test bumped instruments, the new technology utilizes TEL's wafer-prober technology in a controlled environment, and will be extended to involve test devices of all types of interconnect. After a wafer is placed on a thermal chuck with an extremely flat surface, an electrical contact head is aligned to the wafer, and contact is attained through a sheet of contact material from W.L. Gore, called GoreMate. TEL and Motorola will embark on more formal joint development effort to verify the technology and utilize it in production.

Comment:

Has developed a new wafer burn-in technology in collaboration with Motorola Semiconductor Products Sector and Tokyo Electron Ltd

Japan, W.L. Gore & Associates Inc., Motorola Semiconductor Products Sector, Tokyo Electron Ltd.

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Backside emission microscopy pinpoints wafer level defects

Article Abstract:

A technology introduced in late 1996 to thin and check the backside of wafers for defects is the basis for the development of a new technology . Since defects on the wafer emit light isotropically, the new technology removes a calculated thickness of backside silicon and both backside packaging to allow engineers to detect defective emissions from the backside of packaged devices. The thinning of wafers presented a problem and the solution was to develop new probe cards with needles that place a much smaller load on the wafer.

Comment:

A technology developed in 1996 to thin & check backside of wafers for defects is the basis for the dvlpmt of a new technology

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IR method characterizes interstitial oxygen in silicon ingots

Article Abstract:

A process for measuring interstitial oxygen in full-diameter, single- crystal, silicon ingots is discussed. The procedure offers fast feedback for crystal sgrowth process tuning and contributes to full lot characterization without the need for measurements on finished and polished wafers. The results indicate an excellent correlation of crystal measurements with double-side polished wafer measurements.

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