Centralized Supercomputer Support for Magnetic Fusion Energy Research
Article Abstract:
The National Magnetic Fusion Energy Computer Center (NMFECC) uses CRAY-1 high-speed, large memory computers for modeling plasma behavior. Model categories include magnetohydrodynamic, transport, equilibrium, Vlasov, particle, and and Fokker-Planck codes. A CPC 7600 and two CRAY-1's reside at the NMFECC, along with file storage and communications devices. The network allows distributed service and effective use of the main computers using 56-Kbit microwave links or dedicated phone lines. A broad spectrum of specialized software available includes the CTSS interactive operating system, timesharing and batch alternatives, and user support services. Existing computers have computational limits, and there is a need for algorithm optimization using vectorization or finite-element approximations. Future trends to improve the performance for plasma physics and fusion reactors should be in multiprocessor systems. Diagrams illustrate the NMFECC system and communications network. Tables list timing comparisons for algorithm optimizations.
Publication Name: Proceedings of the IEEE
Subject: Electronics
ISSN: 0018-9219
Year: 1984
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Supercomputer requirements for selected disciplines important to aerospace
Article Abstract:
Scientific research in the aerospace fields of turbulence physics, aerodynamics, aerothermodynamics, computational chemistry, and human vision will continue to challenge the capacities of current and future supercomputers. Details of supercomputer utilization in each field are described. Ongoing growth in computational power of such systems has resolved many problems that were once intractable because of computational complexity or extreme amount of time required for solution. The resolution of one generation, though, typically leads to problems of greater computational complexity. Consequently, new technologies, such as the evolving class of massively parallel computer architectures and more efficient parallel algorithms, will be vital to achieve performance in the exaflop-per-second range with memories exceeding petaword size.
Publication Name: Proceedings of the IEEE
Subject: Electronics
ISSN: 0018-9219
Year: 1989
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Scalar supercomputer architecture
Article Abstract:
Several high-performance scalar architectures are described and compared for their execution performance and timing and scheduling constraints. Vector processing, multiprocessor supercomputers typically spend most of their time processing non-vectorizable programs or program components in a scalar mode. Several of these scalar architectures are able to execute multiple instructions in each clock cycle. Example system designs include a horizontal (scientific array) architecture, a polycyclic architecture, a decoupled architecture, and a very-long-instruction-word system, essentially a horizontal system with an advanced compiler for detecting parallelism and generating parallel code. The first Lawrence Livermore Loop code is used to demonstrate the timing and scheduling constraints of each architecture.
Publication Name: Proceedings of the IEEE
Subject: Electronics
ISSN: 0018-9219
Year: 1989
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