Computer-aided design of VLSI FIR filters
Article Abstract:
An application-specific CAD tool is described that produces very high-throughput FIR filters. The benefits of applying bit-level systolic array architecture and application-specific CAD to the problem of filtering is thereby demonstrated. The CAD system reduces the costs of very high-throughput FIR filters with respect to design, fabrication, and operation. An engineer need only specify the filter order N, the input word size, and the output word size to make the tool generate CIF files for a filter system that can process 10 times N million samples per second. The tool enables the implementation of FIR filters that have throughputs exceeding the capabilities of any DSP chip set.
Publication Name: Proceedings of the IEEE
Subject: Electronics
ISSN: 0018-9219
Year: 1987
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VLSI processor for image processing
Article Abstract:
Toshiba's T9506 VLSI processor is appropriate for medical diagnosis and remote sensing, among other image processing applications. Architectural features are: 32-bit fixed point data format; four-stage pipelining and parallel processing; three ports for external data memories and three address generators; on-chip RAM for the writable control storage; and 16-bit data input-output port. The T9506 does FFT, affine transform, spatial filtering, and histogram operation quickly and accurately. It has highly efficient memory address generation architecture and high-speed, high-accuracy features.
Publication Name: Proceedings of the IEEE
Subject: Electronics
ISSN: 0018-9219
Year: 1987
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The graph search machine (GSM): a VLSI architecture for connected speech recognition and other applications
Article Abstract:
The Graph Search Machine (GSM), a VLSI architecture, efficiently computes kernel operations for speech recognition. It uses both on-chip and off-chip memories to increase performance. The basis of operation is a representation of spoken words and grammatical structure in graph-like data structures. The GSM is optimized for aligning and comparing features extracted from a signal. Implementation is on a single VLSI chip in 1.75 micrometer CMOS technology and is a Bell Labs development.
Publication Name: Proceedings of the IEEE
Subject: Electronics
ISSN: 0018-9219
Year: 1987
User Contributions:
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