DSP56200: an algorithm-specific digital signal processor peripheral
Article Abstract:
Processor architecture and two applications of Motorola's DSP56200 algorithm-specific digital signal processing peripheral are discussed. The DSP56200 is a Finite Impulse Response filter and implements the finite sum of products and the least mean square coefficient update algorithms. Performing finite sums of products is the basic operation of digital signal processing. On-chip data and coefficient update algorithms can be used for system scratch-pad memory and provides serial and parallel interfaces to support cascading and communication with a host processor. Echo cancellation and polyphase sample rate conversion filter applications are discussed. Voice-echo canceler versus data-echo canceler needs are analyzed. Both polyphase interpolators and decimators are described.
Publication Name: Proceedings of the IEEE
Subject: Electronics
ISSN: 0018-9219
Year: 1987
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Multiple digital signal processor environment for intelligent signal processing
Article Abstract:
Texas Instrument's TMS32020 signal processing chips are the basis for Odyssey, a multiprocessor board with a novel, expandable, multiple DSP architecture with a symbolic processing host. The host is the TI Explorer, a LISP workstation. Applications are: grammar driven connected speech recognition; neural network simulation; EEG analysis; and generation of speech from general English text with natural language processing. Key features include: 20 million multiply-accumulates per second; 512Kbytes of data space; and expandability to 16 boards on a NuBus host.
Publication Name: Proceedings of the IEEE
Subject: Electronics
ISSN: 0018-9219
Year: 1987
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Digital signal processor for test and measurement environment
Article Abstract:
The TriStar digital signal processor from Tektronix sets a new efficiency standard for the instrument designer. The TriStar is a single-chip implementation that facilitates wave form processing tasks prevalent in a test and measurement environment. It has parallel architecture and a powerful data movement structure. Three units operate concurrently: an instruction fetch unit; an arithmetic unit; and an address computation unit. It offers a cost-effective alternative to dedicated functional processors and bit-slice waveform processing devices.
Publication Name: Proceedings of the IEEE
Subject: Electronics
ISSN: 0018-9219
Year: 1987
User Contributions:
Comment about this article or add new information about this topic:
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