A RAM link for high speed: work on a new, open standard that defines a ring for linking fast memories and processors is well under way
Article Abstract:
The P1596.4 working group is working on a new high-speed RAM interface standard, called RamLink, designed to maximize memory system throughput while keeping latency low, and to minimize the number of devices required for small, high-performance multiprocessor systems. RamLink is intended to provide high performance despite the ineffectiveness of DRAM's internal caching mechanisms, and support flash nonvolatile memory, read-only memory and memory-mapped disks. RamLink's Scalable Coherent Interface (SCI) is designed to provide bus-like services without bused connections, and they use unidirectional, point-to-point differential links at high speeds with a packet-based protocol. With RamLink, all packet activity is scheduled to avoid collisions, and if the RAM cannot return requested data on time, a packet is sent with appropriate status bits to alert the controller to try at a later time.
Publication Name: IEEE Spectrum
Subject: Engineering and manufacturing industries
ISSN: 0018-9235
Year: 1992
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How to program parallel processors
Article Abstract:
A variety of programming techniques now exist to facilitate the structuring of a problem for parallel processing. Eighty to ninety-five percent efficiency is being achieved on systems with several hundred processors. Many of the fundamentals of parallel processing, such as sharing data structures between co-processors and synchronizing access to shared variables, are found in uniprocessor operating systems. Debugging procedures are unique for parallel processing, however, because operations do not occur in the exact same order from run to run. Researchers at the University of Rochester are designing a parallel debugger that records the order of events in a program.
Publication Name: IEEE Spectrum
Subject: Engineering and manufacturing industries
ISSN: 0018-9235
Year: 1987
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