Nitride gate dielectric, poly/W electrode enable 100 nm CMOS

Article Abstract:

Hitachi Ltd researchers have successfully built an ultra-small 0.1 micron complementary metal oxide semiconductor (CMOS) transistor, a revelation made at the 1999 International Electron device Meeting. The invented CMOS transistor utilizes a SiO/SiN stacked gate dielectric with a polysilicon/tungsten gate electrode that allows the equipment to limit electron tunneling, reduce electrical resistance and decrease the pitch or spacing gates while maintaining their contact resistances low.

Japan, C-MOS Integrated Circuits, CMOS integrated circuits, Hitachi Ltd.

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RTO and SiN: an optimum low-cost Si passivation

Article Abstract:

A comprehensive study of rapid, low-cost silicon surface passivation technologies has been conducted. The reuslts reveal that the optimum passivation scheme consists of a thin rapid thermal oxide (RTO) with a SiN cap followed by a very short 730 degrees C anneal. The combination of SiN and RTO can reduce the emitter saturation current density by a factor of 15. It can also reduce the gap in passivation quality between the different nitrides.

United States, Silicon Wafers, Semiconductor wafers

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Nonuniformity of copper electroplating studied

Article Abstract:

Cupricon chief scientist Jacob Jorne made a study of the nonuniformity of copper electroplating for on-chip interconnections. His studies revealed that across-the-wafer nonconformities are related to the resistance of the copper seed layer and the resistance of the electrolyte solution used. These nonuniformities could lead to problems with the subsequent chemical-mechanical polishing process. The gaps or voids can cause problems associated with the trapping of electroplating solution as well as increase the resistance of the interconnect.

Comment:

Chief scientist Jacob Jorne made a study of the nonuniformity of copper electroplating for on-chip interconnections

Semiconductor Devices, New York, Article, Cupricon

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