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Electronics and electrical industries

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Abstracts » Electronics and electrical industries

Design for manufacturability in the sub-lambda domain

Article Abstract:

ASML and Mentor Graphics have unveiled the end results of their collaborative venture during the SPIE conference held in Santa Clara, CA. The products signal the trend towards the integration of imaging technology with design that allows continued extension of optical lithography below the wavelength of the stepper's light source. The environment in the sub-lambda domain necessitates verification beyond design rule checking to examining process windows for resist development, etch microloading and optical proximity effects.

Author: Peters, Laura
Publisher: Reed Business Information, Inc. (US)
Publication Name: Semiconductor International
Subject: Electronics and electrical industries
ISSN: 0163-3767
Year: 2000
Product information, ASML (Tempe, Arizona)

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Thermal processing's tool of choice: single-wafer RTP or Fast Ramp Batch?

Article Abstract:

The semiconductor industry may choose single-wafer rapid thermal processors (RTP) or fast ramp batch as thermal processing tool in making semiconductors. The gap between the two processes, however, is decreasing such that semiconductor firms are having difficulties in selecting which process is more effective. The company should consider factors such as process capability, thermal, cost-of-ownership (COO) and thermal budget before choosing which process to use. Other external factors and trends in the industry such as existing shortening of device lifecycles and technological advancement are pressuring the industry to need faster transfer of thermal processes.

Comment:

Semiconductor ind may choose single-wafer rapid thermal processors or fast ramp batch as thermal processing tool

Author: Peters, Laura
Publisher: Reed Business Information, Inc. (US)
Publication Name: Semiconductor International
Subject: Electronics and electrical industries
ISSN: 0163-3767
Year: 1998
Semiconductor devices, Article

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Choices and challenges for shallow trench isolation

Article Abstract:

The shift to shallow trench isolation (STI) from LOCOS in the fabrication of DRAM devices exposes challenges such as the provision of void-free, seamless gapfill by CVD and uniform planarization by CMP. STI process, which involves silicon etch, oxidation, trench fill by CVD and CMP, results in better scaling and isolation between transistors, although the process is more complicated than conventional methods.

Author: Peters, Laura
Publisher: Reed Business Information, Inc. (US)
Publication Name: Semiconductor International
Subject: Electronics and electrical industries
ISSN: 0163-3767
Year: 1999
Random Access Memory Circuits, RAM (Random access memory)

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