A Processor Family for Personal Computers

Article Abstract:

The Intel 80286 provides direct hardware support for multitasking, memory management, and protection for multiple window user interfaces on personal computers. Multitasking performance is aided by data structures recognized directly by the CPU hardware. The instruction set is broadened from earlier processors. Memory management is simplified by segmentation, memory mapping, and virtual address space partitions. The 80286 can switch tasks in only twenty-one microseconds thanks to its dedicated hardware support. Certain instructions support multiple processor configurations. Multiple protection devices exist, including the virtual address partition, and specific privilege-rights checks. The processor also supports a kernel-based secure operating system to implement sophisticated security policies. Fast memory chips are not required because the chip has a pipeline for four state machines for bus interface, instruction decode, execution, and address decode. The next step in chip evolution will be the 32-bit 80386 processor. Diagrams illustrate memory segmentation, address translation, task management, security methods, system configuration, and performance measurements. Tables also give performance comparisons.

Evaluation, Microprocessor, Product/Service Evaluation, Operating systems (Software), Processor architectures, Memory management, Multiprocessing, Operating System, Personal Computers, Security, Multitasking, 16-Bit, Microprocessors, 32-Bit, 8-Bit, Processor Architecture, Pipelining, Instruction Sets, Process Management, Memory Protection, Virtual Memory, Windowing, Segmentation, Kernel, Paging/Segmentation, 80286

---

Computing image texture features in parallel computers

Article Abstract:

Haralick's texture measures are shown to be amenable to efficient implementation in certain fine-grained architectures. The Send or Random Access Write command is the main operation used to compute these features, and the command is efficiently implemented on a number of today's computers. Computation of gray-level dependency matrices are shown to require random global communication patterns. The classification measures proposed by Haralick and his associates are shown to be good candidates as benchmarks for parallel computer vision architectures.

Architecture, Image processing, Parallel processing

---

Similar abstracts:

• Abstracts: Using the multistage cube network topology in parallel supercomputers. Scattering from a perfectly conducting cube
• Abstracts: The Architecture of the Lisa Personal Computer. Space station data management system architecture
• Abstracts: Digital Scene Simulation: The Synergy of Computer Technology and Human Creativity. part 2 Cardiovascular responses to acceleration stress: a computer simulation
• Abstracts: A comparison of the dynamics of continuous and discrete event systems. Molecular Dynamics and Monte Carlo Simulations in Solid-State and Elementary Particle Physics

This website is not affiliated with document authors or copyright owners. This page is provided for informational purposes only. Unintentional errors are possible.