Pushing the limits of standard CMOS: circuit refinements helped by computer-aided design raise clock rates by an order of magnitude

Article Abstract:

A combination of improved clocking, circuit and logic design enable the clock rates of standard CMOS integrated circuits (ICs) to be pushed to as much as 200-MHz to 1.2-GHz depending upon the device. CMOS process technology offers several benefits in the implementation of very-large-scale integration ICs, including low power demand, 'wide noise margin,' and low cost. Unfortunately, CMOS is slow compared to other process technologies. The new, faster CMOS technology employs a true single-phase clock, optimization of device sizes for speed and precharged logic style to increase performance. The main trade-off is a doubling of the circuit area required. The new technology is best suited for applications with simple algorithms. Details of the high-speed CMOS technology are discussed.

Industrial research, Product introduction, Performance improvement (Computers), Research and Development, New Technique, Performance Improvement, Clocks

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The Case For CMOS

Article Abstract:

The rise of very-large-scale integration has shown that CMOS is as reliable and cost-efficient as NMOS and bipolar technologies. CMOS also uses less current and allows greater ease of circuit design. Diagrams show the design of a multiple-input logic gate using static or dynamic CMOS logic. In order to optimize processing, industries are making an effort to convert NMOS production to CMOS, while minimizing production feature size. The tradeoffs involve circuit performance, layout density, fabrication cost, and tolerence to latchup. Models illustrate many possible designs of CMOS circuits using n and p well and channel design, including stacking and fabrication in silicon-on-oxide configuration. A table from a Japanese report summarizes five 8-kb-by-8-bit static RAMs.

Semiconductor devices, Electronic components, Integrated circuit fabrication, Electronics, Memory, RAM, RAM (Random access memory), Design, Microelectronics, Hardware, Gate arrays, Semiconductor Device, N-Channel Metal Oxide Semiconductors, MOS Integrated Circuits, Gates, Bipolar Integrated Circuits, VLSI, Circuitry, Static Cell, Packaging Density, Miniaturization

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The faults in CMOS IC fault testing

Article Abstract:

The most widely used method of testing complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) neglects the primary causes of CMOS IC failure, while focusing on 'stuck-at' faults. Sandia (Albuquerque, NM) uses a method that can detect gate oxide shorts, bridges, and parasitic transistor leakage, and can also detect stuck-at faults as well. The IDDQ testing method measures the power supply current during the non-switching state of the circuit, indicating a defect directly. The method takes advantage of the low current of less than 10 nanoamperes typical for CMOS during the quiescent state.

Product information, Tests, Power supplies (Computers), Testing, Power Supply, Sandia National Laboratory

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