The challenges of 300 mm wafer cleaning

Article Abstract:

Scaling existing batch wet technologies can become more difficult late in the 300 mm era when more than 90% yields on 130 nm and 100 nm devices are to be required. Traditional Aqueus-based chemistries can attain the particle, metal, roughness and oxide etch uniformity needs for pre-gate cleans predicted in the SIA roadmap, but finds difficulty during scaling. Apart from merely scaling current batch wet technologies, the process is aggravated by integrating to the preceding and succeeding processes, at the same time, cutting the environmental impact, enhancing safety and cutting cost of ownership for each process. An alternative to batch wet cleaning would be to move to 180 nm devices and 300 mm wafers to meet key challenges not achievalbe by the current process.

Comment:

Scaling current batch wet technologies are more difficult in 300 mm era when over 90% yields on 130 nm & 100 nm are required

Semiconductor Devices

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Dual-damascene aluminum process developed

Article Abstract:

IBM and the IBM/Siemens DRAM Development Alliance have developed a four-level interconnect process intended for 1 Gb DRAMs. The unique process uses aluminum wiring pattened in a dual-damascene approach, resulting in up to 10% savings in chip area compared with a conventional three-level approach. Dual-damascene aluminum offers superior electromigration and stress migration performance compared with aluminum reactive ion etching (RIE), eliminating the need to use copper for enhanced reliability.

Comment:

Develops a four-level interconnect process intended for 1 Gb DRAMs

Random Access Memory Circuits, International Business Machines Corp., RAM (Random access memory)

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