Systolic Array Simulation for Quantification of Speed-Area Parameters
Article Abstract:
A comprehensive circuit simulation of a VLSI (Very Large Scale Integration) systolic array processor for band matrix triangulation is developed. A systolic array structure is composed of simple, regularly connected processing elements configured to rapidly triangulate large, band form, linear equation systems. I-O circuit models are developed which provide operand demultiplexing-multiplexing necessary to convert serial operand I-O, at the chip boundaries, to a parallel broadcasting of operands to-from the processing cells. The complete layout of the model is a tessellated design of processing elements and I-O modules which ideally will be fabricated on a single chip. Fundamental design parameters which may be manipulated in the simulation include a scalable lithographic linewidth, the number of bits per word and matrix bandwidth. Comparisons are made of total propagation delay time and chip size versus matrix bandwidth. These results, in turn, lead to an assessment of the feasibility and advantages of this type of special purpose VLSI computing structure. (Reprinted by Permission of Publisher).
Publication Name: SIMULATION
Subject: Engineering and manufacturing industries
ISSN: 0037-5497
Year: 1985
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Behavioral simulation of array processors in the APES environment
Article Abstract:
APES is an integrated, flexible CAD environment developed for behavioral design, simulation and evaluation of array processor architectures. This paper discusses in detail the core of the system, i.e. the behavioral simulator. This is an interactive subsystem which allows one to set up and run the simulation of the array using the definition of the array architecture supplied by the user. This task computes the output results of the whole array, of each processing element and of each functional unit. The concept of time is also defined and handled by the simulator so to allow subsequent performance evaluation. Functions are available for tracing, for inserting break-points, for step-by-step execution and for selection of display format. The simulator interacts with the other modules of APES (e.g. the Fault Injector, the Reconfiguration Manager) and produces results which can also be post-processed by other modules of APES (e.g. the Diagnostic Evaluator) to aid the designer in evaluating particular characteristics of the architecture. (Reprinted by permission of the publisher.)
Publication Name: SIMULATION
Subject: Engineering and manufacturing industries
ISSN: 0037-5497
Year: 1992
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