Experience with Pipelined Multiple Instruction Streams

Article Abstract:

The Heterogeneous Element Processor (HEP) computer consists of one or more pipelined multiple instruction-multiple data (MIMD) Process Execution Modules (PEM) that share memory. The memory of the HEP system is program memory, register memory, constant memory, and data memory. Fortran is used in a modified form with the system. The machine can minimize turnaround time by partitioning work on function or on data across multiple instruction streams. Several categories of applications programs are possible. 'Dusty deck' Fortran programs are originally written for a sequential processor and require mechanical parallelization for optimization. The vector program can compare MIMD performance with single instruction-MD performance. A distinct class of programs is nonvectorizable, and MIMD parallelization is more natural. Graphs show the pipelines in the machine are fully utilized for twenty or more processes. Diagrams illustrate MIMD and SIMD architectures as well as the principle pipelines in the HEP.

Parallel processing, Multiprocessing, Array Processor, MIMD

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Reduced instruction set computer architecture

Article Abstract:

The general trend in CPU architecture has been toward complexity, with larger instruction sets, multiple addressing modes, and specialized registers. The relatively new RISC CPUs (characterized by one instruction per cycle, register-to-register operations, simple address modes, and simple instruction formats) are challenging this design philosophy with numerous or optimized register usage, reduced instruction sets, and pipelining. Performance benefits include: more efficient compilers; no microcode usage; more effective pipelining; and improved interrupt response. Examples of RISC systems are the experimental Berkeley RISC and the commercial MIPS R2000.

Computers, Microprocessor, Digital computers, Microcomputer, Computer Design, Programming, Registers, RISC, RISC processors

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Parallel bit-level pipelined VLSI designs for high-speed signal processing

Article Abstract:

Six bit-level pipelined VLSI designs for high-speed signal processing are explored. The issues in designing such fully pipelined architectures are: clock skew; clock distribution networks; buffering; timing simulation; area overhead from pipelining; and testing. Designs now fabricated in CMOS technology include: a multiplier; Finite Impulse Response (FIR) filter block; and a multi-channel, multiply-accumulate-add chip. Test results for functionality and speed are given. The chips presented are examples of building block FIR implementing algorithms, in which throughput and real-time operation are major concerns and latency is not a critical factor.

Semiconductors and related devices, Circuit design, Very large scale integration, Signal processing, Applications, Very-Large-Scale Integration, technical

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